1. Field of the Invention
The present invention generally relates to integrated circuit capacitor components and, in particular, to a method of fabricating a shallow capacitor cell having multiple grooves, particularly useful for dynamic random access memory (DRAM) integrated circuits.
2. Description of the Related Art
Computer memory integrated circuits often use random access memory (RAM) components because of their versatility and the high density of memory cells which can be achieved, particularly in metal-oxide semiconductor (MOS) die. Basically, a cell for storing a bit of digital data uses a single transistor and a storage capacitor. The digital information is held as a charge on the capacitor and is addressed through the transistor. An array of such cells are connected by bit lines and word lines accessed via an address decoder.
Capacitor data storage suffers from charge loss due to leakage currents. Therefore, all the storage capacitors in the array are occasionally refreshed to drive the capacitors back to a full logic level representing a stored bit of data; hence, the derivation of the name "dynamic RAM" or DRAM.
A major operational problem of the DRAM is known as the "soft failure," i.e., the spontaneous flipping of a memory bit while the integrated circuit basically is operating properly. It has been found that this phenomena is attributable to random alpha particles (helium nuclei). Alpha particles can come from cosmic rays reacting with the silicon of the die. It has also been discovered that the alpha particles are often generated by the integrated circuit package materials. The traveling particles have an ionization wake which leaves behind a trail of electronhole pairs in the die. The holes, if in proximity to a storage capacitor, can result in a charge loss sufficient to cause a soft failure. Whatever the source, the alpha particles are known to generate an upset charge as they travel through the die which may cause any cell in their general path to fail.
Several proposals have been offered as solutions to the soft failure problem. Covering the die surface with a silicone protecting material provides some reduction. Another technique is to increase the capacitor size to accommodate any such charge loss or gain occasioned by the incursion of an alpha particle (10.sup.6 electrons).
One type of structure to increase efficiently the storage capacity is proposed by Sunami, et al, "A Corrugated Capacitor Cell (CCC)," as published in the IEEE Transactions on Electron Devices, Vol. ED-31, No. 6, June 1984, pp. 746-753. Sunami, et al, proposes the use of a deep trench etched several microns into the silicon substrate. Storage capacitance is increased by forming the capacitor plate on the side walls of the trench in addition to the planar surface of the substrate. As cell density increases, however, the trench must be made deeper to give the same required storage capacitance. This, in turn, causes manufacturing problems due to the depth of silicon that must be etched. Additionally, it becomes difficult to put DRAM cells in complementary metal-oxide semiconductor (CMOS) wells because the capacitor grooves would penetrate through wells which are processable generally to about 4 microns deep. DRAMs in CMOS wells are more resistant to alpha particle induced soft errors. Therefore, there is a benefit to making a shallow capacitor that can fit in a CMOS well.
With respect to DRAM devices, standard 16-pin integrated circuit packing approaches maximum density at the 256k size. Hence, there is a need in the integrated circuit field for improved storage capacitor structures, particularly for increasing capacitance without increasing overall physical size.